RSPIのMISOA信号とSPDRより読み取った値が異なってしまいます。

お世話になっております。

RX113のRSPIで、富士通のFRAMをスレーブデバイスとして接続し、通信を行っております。

無事にFRAMにステータスリードのコマンドを送信して、下図の通りバス上では正しいレスポンス(0x10)が返ってきました。

しかし、読み取ったSPDRの値はなぜか(0xFF)という値でした。

  

送受信のソースは次の通りです。

//
// FRAM ステータスレジスタ 読み込み
//
  Y_RSPI0_Start();
  PORTC.PODR.BIT.B4 = 0;           // チップセレクト -> FRAM

  while(RSPI0.SPSR.BIT.SPTEF == 0);
  // RDSR コマンド送信 ( 送信バイト数:1、データ:0x05 )

  RSPI0.SPDR.WORD.H = 0x0005;       // データの送信
  while(RSPI0.SPSR.BIT.IDLNF == 1);     // 送信完了待ち
  RSPI0.SPDR.WORD.H = 0x0000;       //  レスポンス受信用のクロック送出
  while(RSPI0.SPSR.BIT.IDLNF == 1);     // 送信完了待ち


  while(RSPI0.SPSR.BIT.SPRF == 0);      // 受信バッファフルの確認
  FRAM_READ_STR = RSPI0.SPDR.WORD.H;

  PORTC.PODR.BIT.B4 = 1;           // チップセレクト 解除
  Y_RSPI0_Stop();

 

バス上の信号(0x10)が何故0xFFになるのか、何処に原因があるのかわかりません。

リードするタイミングでしょうか。お手数をおかけしますが、ご教示願います。

 

※ コードの作成では、過去スレッドのつくしさんの回答を参考にさせていただきました。

  • In reply to LEON:

    LEON様

    お忙しいところ、ご返信ありがとうございます。<m(__)m>

    試したいのですが、他のコマンドをリード・ライトする関数はまだ作成していないのです。
    ステータスレジスタ用の関数から始めて、そこで足踏みしているという状態です。
    もう情けなくて泣きたいです。

    一つ確認しておきたいのですが、CPUの端子には、同じ機能を持つ端子があります。

    RSPCKA(RX113):P15,PB0,PC5,PE3,P51
    MISOA(RX113):P17,PA3,PC7,PE5,P52
    MOSIA(RX113):P16,PA6,PC6,PE4,P50

    もしかして、これらの組み合わせでやってはいけない組み合わせがあったりするのでしょうか。
    あらためて番号を眺めていましたら、それぞれ近い数字があるため、まさかと思っているのですが…
  • In reply to パールマン:

    LEONです。
    回路図上、外部FRAMとCPU端子の接続はどのようになっていますか?
    接続状況に合わせ、マルチファンクションピンコントローラ(MPC)のレジスタ設定をご確認下さい。
    ─────────────────────────────────────────────────────────────────────
     RSPCK MOSIA MISOA   : MPCのレジスタ設定  *=0~7のどれか。今回は0かな
    ─────────────────────────────────────────────────────────────────────
    ・PB0  PA6  PA3の場合 : PB*PFS.PSEL = 01101b、 PA*PFS.PSEL = 01101b
    ・PC5  PC6  PC7の場合 : PC*PFS.PSEL = 01101b
    ・PE3  PE4  PE5の場合 : PE*PFS.PSEL = 01101b
    ・P51  P50  P52の場合 : P5*PFS.PSEL = 01101b 100pin
    ・P15  P16  P17の場合 : P1*PFS.PSEL = 01101b
    ─────────────────────────────────────────────────────────────────────
    上記5つ中の何れか一つの結線、設定になろうかと思います。
  • In reply to LEON:

    LEON様
    御回答ありがとうございます。
    只今スマートフォンで閲覧させて頂いておりますが、どうも嫌な予感が的中した可能性が高いです。
    帰宅次第、ハードウェアマニュアルを確認します。
  • In reply to LEON:

    LEON様
    お世話になっております。
    どうやら接続は問題ないようです。
    CPUとの接続は、次の通りです。

    端子設定
     RSPCKA: P51 (41)
     MOSIA: P50 (42)
     MISOA: P52 (40)

    マルチファンクションピンコントローラ(MPC)に関係する設定

    /* Set RSPCKA pin */
    MPC.P51PFS.BYTE = 0x0DU;
    PORT5.ODR0.BYTE &= 0xF7U;
    PORT5.ODR0.BYTE |= 0x04U;
    PORT5.PMR.BYTE |= 0x02U;

    /* Set MOSIA pin */
    MPC.P50PFS.BYTE = 0x0DU;
    PORT5.ODR0.BYTE &= 0xFDU;
    PORT5.ODR0.BYTE |= 0x01U;
    PORT5.PMR.BYTE |= 0x01U;

    /* Set MISOA pin */
    MPC.P52PFS.BYTE = 0x0DU;
    PORT5.ODR0.BYTE &= 0xDFU;
    PORT5.ODR0.BYTE |= 0x10U;
    PORT5.PMR.BYTE |= 0x04U;


    このままでは開発作業が一歩も進まないので、データの読み込みは課題としておき、
    データのやり取りが正しく行われていることをロジアナ上で確認しておくことにしました。
  • In reply to パールマン:

    パールマン様
    CPU違いによる設定や処理の相違、誤記等は申し訳なかったです。無事解決されることを願っています。
    私の方はSH2Aにて、RSPIによるFlash制御、ADC,DAC制御を実現していました。
  • In reply to リカルド:

    パールマンさん、こんにちは。どうも始めまして。藁を少し足してみました。
    ・マイコンの破損/不良
    ・基板の破損/不良
    ・基板のパターン設計のミス
    RX113とFRAMを切り離して、MISOA信号線のロジアナを繋いでいた箇所をLowに落として、マイコンのMISOA端子を単なる入力ポートに設定して読んでみる、というのを試すのはどうでしょうか?

    パールマンさんwrote:
    >MISOAの配線がはずれているのか?とも考えましたが、それもないようです。
    >※ バスに正しい信号が出ていて、マイコンに入っていないとしたら、配線しか疑うところがない。
    >困った。

    リカルドさんwrote:
    >>困った。
    > RX113もRSPIも知らないけど、困っているようだから。
    > 「藁をも掴む」の藁回答です。
    >・通信速度を下げる。速い方が良いと言うので安易に速くすると、トラブルの元
    >・プルアップが必要な信号ではないか
    >・電源電圧と速度の依存性は無いか
    >・CPUの処理速度が速いと、ステータスが確定する前のステータスを読む事がある。 ...以降略...
    >・通信の場合、最初のデータはゴミの事が多い。受信だったら、ゴミデータを読んでデータが空になった後が正しいデータとか。 ...以降略...

  • In reply to NoMaY:

    NoMaY様
    お世話になっております。
    配線については私も自分自身をかなり疑い、調べてみました。
    しかし、配線は問題がありませんでした。試作といいましてもまだ開発試作の段階なので、万能基板で製作しています。これが製品試作だったら大変ですが…

    次にためしたこと、RSPIのループバック機能を生かしたループバックテスト。
    これも問題なし。(送信データは読めた)

    次にためしたこと、ポートセットの変更。
    RX113には、MOSIAとMISOAとRSPCKAの組み合わせが5組ありまして、
    別の組み合わせに変更してみました。
    それでも謎現象のFFになってしまう。 よって、CPUの破損の可能性は無い。あってもかなり低い。

    LEONさんがご指摘されているような何らかの設定の誤りのような気もするのですが…
  • In reply to パールマン:

    そうでしたか。では、次は、コード生成で生成した割り込みを使うコードを素直に使ってみる、というあたりをもう一度でしょうか? 過去の別スレッドの投稿も読ませて頂きましたが、サンプルプログラムもコード生成もうまく動かなかった(動くようにすることが出来なかった)からといって、おもむろにハードウェアマニュアルからコードを書き起こすのは、少々早計だったのではないかなぁ???という気がしなくもないです、、、

    で、コード生成されたソースのAPIの使い方が分からないなり、そのやり方でもうまく動かないなり、というあたりで、プロジェクトのファイル一式をzipファイルに固めて添付して質問されてみてはどうでしょうか?

    パールマンさんも気付いておられると思いますが、コード生成で生成したソースは、ハードウェアマニュアルのレジスタ設定に薄い皮を被せた程度と言ってしまって構わないような、以下のようなペラペラなソースですよね。活用しない手は無いような気がします。(それに何より、コード生成したソース/プロジェクトがそのままで動かないとなれば(もちろん必要なSendなりReceiveなり(とStart)のコードは追加した上でのことですが)、堂々とRenesas社の会社としての問い合わせ窓口に質問出来ますし、、、)
    r_cg_rspi.c

    2275.r_cg_rspi.c.txt
    /***********************************************************************************************************************
    * DISCLAIMER
    * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
    * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
    * applicable laws, including copyright laws. 
    * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
    * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
    * NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
    * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
    * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
    * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
    * of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
    * following link:
    * http://www.renesas.com/disclaimer
    *
    * Copyright (C) 2014, 2016 Renesas Electronics Corporation. All rights reserved.
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    * File Name    : r_cg_rspi.c
    * Version      : Code Generator for RX113 V1.02.05.01 [11 Nov 2016]
    * Device(s)    : R5F51138AxFP
    * Tool-Chain   : CCRX
    * Description  : This file implements device driver for RSPI module.
    * Creation Date: 2017/05/16
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    Pragma directive
    ***********************************************************************************************************************/
    /* Start user code for pragma. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    
    /***********************************************************************************************************************
    Includes
    ***********************************************************************************************************************/
    #include "r_cg_macrodriver.h"
    #include "r_cg_rspi.h"
    /* Start user code for include. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    #include "r_cg_userdefine.h"
    
    /***********************************************************************************************************************
    Global variables and functions
    ***********************************************************************************************************************/
    uint32_t * gp_rspi0_tx_address;         /* RSPI0 transmit buffer address */
    uint16_t   g_rspi0_tx_count;            /* RSPI0 transmit data number */
    uint32_t * gp_rspi0_rx_address;         /* RSPI0 receive buffer address */
    uint16_t   g_rspi0_rx_count;            /* RSPI0 receive data number */
    uint16_t   g_rspi0_rx_length;           /* RSPI0 receive data length */
    /* Start user code for global. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    
    /***********************************************************************************************************************
    * Function Name: R_RSPI0_Create
    * Description  : This function initializes the RSPI0 module.
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    void R_RSPI0_Create(void)
    {
        /* Disable RSPI interrupts */
        IEN(RSPI0,SPTI0) = 0U;
        IEN(RSPI0,SPRI0) = 0U;
        IEN(RSPI0,SPEI0) = 0U;
        IEN(RSPI0,SPII0) = 0U;
    
        /* Cancel RSPI module stop state */
        MSTP(RSPI0) = 0;
    
        /* Disable RSPI function */
        RSPI0.SPCR.BIT.SPE = 0U;
    
        /* Set control registers */
        RSPI0.SPDCR.BYTE = _00_RSPI_ACCESS_WORD | _00_RSPI_FRAMES_1;
        RSPI0.SPSCR.BYTE = _00_RSPI_SEQUENCE_LENGTH_1;
        RSPI0.SPCR2.BYTE = _00_RSPI_PARITY_DISABLE;
        RSPI0.SPCMD0.WORD = _0001_RSPI_RSPCK_SAMPLING_EVEN | _0000_RSPI_RSPCK_POLARITY_LOW | 
                            _0400_RSPI_DATA_LENGTH_BITS_8 | _0000_RSPI_MSB_FIRST;
    
        /* Set SPEI0, SPRI0, SPTI0 and SPII0 priority level */
        IPR(RSPI0,SPTI0) = _0F_RSPI_PRIORITY_LEVEL15;
    
        /* Set RSPCKA pin */
        MPC.P51PFS.BYTE = 0x0DU;
        PORT5.ODR0.BYTE &= 0xF3U;
        PORT5.PMR.BYTE |= 0x02U;
    
        /* Set MOSIA pin */
        MPC.P50PFS.BYTE = 0x0DU;
        PORT5.ODR0.BYTE &= 0xFCU;
        PORT5.PMR.BYTE |= 0x01U;
    
        /* Set MISOA pin */
        MPC.P52PFS.BYTE = 0x0DU;
        PORT5.ODR0.BYTE &= 0xCFU;
        PORT5.PMR.BYTE |= 0x04U;
    
        RSPI0.SPCR.BYTE = _01_RSPI_MODE_CLOCK_SYNCHRONOUS | _00_RSPI_FULL_DUPLEX_SYNCHRONOUS | _00_RSPI_SLAVE_MODE;
    }
    
    /***********************************************************************************************************************
    * Function Name: R_RSPI0_Start
    * Description  : This function starts the RSPI0 module operation.
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    void R_RSPI0_Start(void)
    {
        volatile uint8_t dummy;
    
        /* Enable RSPI interrupts */
        IEN(RSPI0,SPTI0) = 1U;
        IEN(RSPI0,SPRI0) = 1U;
        IEN(RSPI0,SPEI0) = 1U;
        IEN(RSPI0,SPII0) = 1U;
    
        /* Clear error sources */
        dummy = RSPI0.SPSR.BYTE;
        RSPI0.SPSR.BYTE = 0xA0U;
    
        /* Disable idle interrupt */
        RSPI0.SPCR2.BIT.SPIIE = 0U;
    }
    
    /***********************************************************************************************************************
    * Function Name: R_RSPI0_Stop
    * Description  : This function stops the RSPI0 module operation.
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    void R_RSPI0_Stop(void)
    {
        /* Disable RSPI interrupts */
        IEN(RSPI0,SPTI0) = 0U;
        IEN(RSPI0,SPRI0) = 0U;
        IEN(RSPI0,SPEI0) = 0U;
        IEN(RSPI0,SPII0) = 0U;
    
        /* Disable RSPI function */
        RSPI0.SPCR.BIT.SPE = 0U;
    }
    /***********************************************************************************************************************
    * Function Name: R_RSPI0_Send_Receive
    * Description  : This function sends and receives RSPI0 data.
    * Arguments    : tx_buf -
    *                    transfer buffer pointer (not used when data is handled by DTC)
    *                tx_num -
    *                    buffer size
    *                rx_buf -
    *                    receive buffer pointer (not used when data is handled by DTC)
    * Return Value : status -
    *                    MD_OK or MD_ARGERROR
    ***********************************************************************************************************************/
    MD_STATUS R_RSPI0_Send_Receive(uint32_t * const tx_buf, uint16_t tx_num, uint32_t * const rx_buf)
    {
        MD_STATUS status = MD_OK;
    
        if (tx_num < 1U)
        {
            status = MD_ARGERROR;
        }
        else
        {
            /* Initialize the global counters */
            gp_rspi0_tx_address = tx_buf;
            g_rspi0_tx_count = tx_num;
            gp_rspi0_rx_address = rx_buf;
            g_rspi0_rx_length = tx_num;
            g_rspi0_rx_count = 0U;
    
            /* Clear SPE bit to ensure transmit buffer empty interrupt be generated
               when state of SPE bit changing from 0 to 1 is satisfied later        */
            if(1U == RSPI0.SPCR.BIT.SPE)
            {
                RSPI0.SPCR.BIT.SPE = 0U;
            }
    
            /* Enable transmit interrupt */
            RSPI0.SPCR.BIT.SPTIE = 1U;
    
            /* Enable receive interrupt */
            RSPI0.SPCR.BIT.SPRIE = 1U;
    
            /* Enable error interrupt */
            RSPI0.SPCR.BIT.SPEIE = 1U;
    
            /* Enable RSPI function */
            RSPI0.SPCR.BIT.SPE = 1U;
        }
    
        return (status);
    }
    
    /* Start user code for adding. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    


    r_cg_rspi_user.c

    4341.r_cg_rspi_user.c.txt
    /***********************************************************************************************************************
    * DISCLAIMER
    * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
    * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
    * applicable laws, including copyright laws. 
    * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
    * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
    * NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
    * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
    * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
    * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
    * of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
    * following link:
    * http://www.renesas.com/disclaimer
    *
    * Copyright (C) 2014, 2016 Renesas Electronics Corporation. All rights reserved.
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    * File Name    : r_cg_rspi_user.c
    * Version      : Code Generator for RX113 V1.02.05.01 [11 Nov 2016]
    * Device(s)    : R5F51138AxFP
    * Tool-Chain   : CCRX
    * Description  : This file implements device driver for RSPI module.
    * Creation Date: 2017/05/16
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    Pragma directive
    ***********************************************************************************************************************/
    /* Start user code for pragma. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    
    /***********************************************************************************************************************
    Includes
    ***********************************************************************************************************************/
    #include "r_cg_macrodriver.h"
    #include "r_cg_rspi.h"
    /* Start user code for include. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    #include "r_cg_userdefine.h"
    
    /***********************************************************************************************************************
    Global variables and functions
    ***********************************************************************************************************************/
    extern uint32_t * gp_rspi0_tx_address;         /* RSPI0 transmit buffer address */
    extern uint16_t   g_rspi0_tx_count;            /* RSPI0 transmit data number */
    extern uint32_t * gp_rspi0_rx_address;         /* RSPI0 receive buffer address */
    extern uint16_t   g_rspi0_rx_count;            /* RSPI0 receive data number */
    extern uint16_t   g_rspi0_rx_length;           /* RSPI0 receive data length */
    /* Start user code for global. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    
    /***********************************************************************************************************************
    * Function Name: r_rspi0_transmit_interrupt
    * Description  : None
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    #if FAST_INTERRUPT_VECTOR == VECT_RSPI0_SPTI0
    #pragma interrupt r_rspi0_transmit_interrupt(vect=VECT(RSPI0,SPTI0),fint)
    #else
    #pragma interrupt r_rspi0_transmit_interrupt(vect=VECT(RSPI0,SPTI0))
    #endif
    static void r_rspi0_transmit_interrupt(void)
    {
        uint16_t frame_cnt;
            
        for (frame_cnt = 0U; frame_cnt < (_00_RSPI_FRAMES_1 + 1U); frame_cnt++)
        {
            if (g_rspi0_tx_count > 0U)
            {
                /* Write data for transmission */
                RSPI0.SPDR.WORD.H = (*(uint16_t*)gp_rspi0_tx_address);
                gp_rspi0_tx_address++;
                g_rspi0_tx_count--;
            }
            else
            {
                /* Disable transmit interrupt */
                RSPI0.SPCR.BIT.SPTIE = 0U;
                r_rspi0_callback_transmitend();
                break;
            }
        }
    }
    /***********************************************************************************************************************
    * Function Name: r_rspi0_receive_interrupt
    * Description  : None
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    #if FAST_INTERRUPT_VECTOR == VECT_RSPI0_SPRI0
    #pragma interrupt r_rspi0_receive_interrupt(vect=VECT(RSPI0,SPRI0),fint)
    #else
    #pragma interrupt r_rspi0_receive_interrupt(vect=VECT(RSPI0,SPRI0))
    #endif
    static void r_rspi0_receive_interrupt(void)
    {
        uint16_t frame_cnt;
        
        for (frame_cnt = 0U; frame_cnt < (_00_RSPI_FRAMES_1 + 1U); frame_cnt++)
        {
            if (g_rspi0_rx_length > g_rspi0_rx_count)
            {
                *(uint16_t *)gp_rspi0_rx_address = RSPI0.SPDR.WORD.H;
                gp_rspi0_rx_address++;
                g_rspi0_rx_count++;
    
                if (g_rspi0_rx_length == g_rspi0_rx_count)
                {
                    /* Disable receive interrupt */
                    RSPI0.SPCR.BIT.SPRIE = 0U;
                    r_rspi0_callback_receiveend();
                    break;
                }
            }
        }
    }
    /***********************************************************************************************************************
    * Function Name: r_rspi0_error_interrupt
    * Description  : None
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    #if FAST_INTERRUPT_VECTOR == VECT_RSPI0_SPEI0
    #pragma interrupt r_rspi0_error_interrupt(vect=VECT(RSPI0,SPEI0),fint)
    #else
    #pragma interrupt r_rspi0_error_interrupt(vect=VECT(RSPI0,SPEI0))
    #endif
    static void r_rspi0_error_interrupt(void)
    {
        uint8_t err_type;
    
        /* Disable RSPI function */
        RSPI0.SPCR.BIT.SPE = 0U;
    
        /* Disable transmit interrupt */
        RSPI0.SPCR.BIT.SPTIE = 0U;
    
        /* Disable receive interrupt */
        RSPI0.SPCR.BIT.SPRIE = 0U;
    
        /* Disable error interrupt */
        RSPI0.SPCR.BIT.SPEIE = 0U;
    
        /* Disable idle interrupt */
        RSPI0.SPCR2.BIT.SPIIE = 0U;
    
        /* Clear error sources */
        err_type = RSPI0.SPSR.BYTE;
        RSPI0.SPSR.BYTE = 0xA0U;
    
        if (err_type != 0U)
        {
            r_rspi0_callback_error(err_type);
        }
    }
    /***********************************************************************************************************************
    * Function Name: r_rspi0_callback_transmitend
    * Description  : This function is a callback function when RSPI0 finishes transmission.
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    static void r_rspi0_callback_transmitend(void)
    {
        /* Start user code. Do not edit comment generated here */
        /* End user code. Do not edit comment generated here */
    }
    
    /***********************************************************************************************************************
    * Function Name: r_rspi0_callback_receiveend
    * Description  : This function is a callback function when RSPI0 finishes reception.
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    static void r_rspi0_callback_receiveend(void)
    {
        /* Start user code. Do not edit comment generated here */
        /* End user code. Do not edit comment generated here */
    }
    
    /***********************************************************************************************************************
    * Function Name: r_rspi0_callback_error
    * Description  : This function is a callback function when RSPI0 error occurs.
    * Arguments    : err_type -
    *                    error type value
    * Return Value : None
    ***********************************************************************************************************************/
    static void r_rspi0_callback_error(uint8_t err_type)
    {
        /* Start user code. Do not edit comment generated here */
        /* End user code. Do not edit comment generated here */
    }
    
    
    /* Start user code for adding. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    


    r_cg_rspi.h

    5417.r_cg_rspi.h.txt
    /***********************************************************************************************************************
    * DISCLAIMER
    * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
    * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
    * applicable laws, including copyright laws. 
    * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
    * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
    * NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
    * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
    * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
    * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
    * of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
    * following link:
    * http://www.renesas.com/disclaimer
    *
    * Copyright (C) 2014, 2016 Renesas Electronics Corporation. All rights reserved.
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    * File Name    : r_cg_rspi.h
    * Version      : Code Generator for RX113 V1.02.05.01 [11 Nov 2016]
    * Device(s)    : R5F51138AxFP
    * Tool-Chain   : CCRX
    * Description  : This file implements device driver for RSPI module.
    * Creation Date: 2017/05/16
    ***********************************************************************************************************************/
    #ifndef RSPI_H
    #define RSPI_H
    
    /***********************************************************************************************************************
    Macro definitions (Register bit)
    ***********************************************************************************************************************/
    /*
        RSPI Control Register (SPCR)
    */
    /* RSPI Mode Select (SPMS) */
    #define _00_RSPI_MODE_SPI                       (0x00U) /* SPI operation (four-wire method) */
    #define _01_RSPI_MODE_CLOCK_SYNCHRONOUS         (0x01U) /* Clock synchronous operation (three-wire method) */
    /* Communications Operating Mode Select (TXMD) */
    #define _00_RSPI_FULL_DUPLEX_SYNCHRONOUS        (0x00U) /* Full-duplex synchronous serial communications */
    #define _02_RSPI_TRANSMIT_ONLY                  (0x02U) /* Serial communications with transmit only operations */
    /* Mode Fault Error Detection Enable (MODFEN) */
    #define _00_RSPI_MODE_FAULT_DETECT_DISABLED     (0x00U) /* Disables the detection of mode fault error */
    #define _04_RSPI_MODE_FAULT_DETECT_ENABLED      (0x04U) /* Enables the detection of mode fault error */
    /* RSPI Master/Slave Mode Select (MSTR) */
    #define _00_RSPI_SLAVE_MODE                     (0x00U) /* Slave mode */
    #define _08_RSPI_MASTER_MODE                    (0x08U) /* Master mode */
    /* RSPI Error Interrupt Enable (SPEIE) */
    #define _00_RSPI_ERROR_INTERRUPT_DISABLED       (0x00U) /* Disables the generation of RSPI error interrupt */
    #define _10_RSPI_ERROR_INTERRUPT_ENABLED        (0x10U) /* Enables the generation of RSPI error interrupt */
    /* RSPI Transmit Interrupt Enable (SPTIE) */
    #define _00_RSPI_TRANSMIT_INTERRUPT_DISABLED    (0x00U) /* Disables the generation of RSPI transmit interrupt */
    #define _20_RSPI_TRANSMIT_INTERRUPT_ENABLED     (0x20U) /* Enables the generation of RSPI transmit interrupt */
    /* RSPI Function Enable (SPE) */
    #define _00_RSPI_FUNCTION_DISABLED              (0x00U) /* Disables the RSPI function */
    #define _40_RSPI_FUNCTION_ENABLED               (0x40U) /* Enables the RSPI function */
    /* RSPI Receive Interrupt Enable (SPRIE) */
    #define _00_RSPI_RECEIVE_INTERRUPT_DISABLED     (0x00U) /* Disables the generation of RSPI receive interrupt */
    #define _80_RSPI_RECEIVE_INTERRUPT_ENABLED      (0x80U) /* Enables the generation of RSPI receive interrupt */
    
    /*
        RSPI Slave Select Polarity Register (SSLP)
    */
    /* SSL0 Signal Polarity Setting (SSL0P) */
    #define _00_RSPI_SSL0_POLARITY_LOW              (0x00U) /* SSL0 signal is active low */
    #define _01_RSPI_SSL0_POLARITY_HIGH             (0x01U) /* SSL0 signal is active high */
    /* SSL1 Signal Polarity Setting (SSL1P) */
    #define _00_RSPI_SSL1_POLARITY_LOW              (0x00U) /* SSL1 signal is active low */
    #define _02_RSPI_SSL1_POLARITY_HIGH             (0x02U) /* SSL1 signal is active high */
    /* SSL2 Signal Polarity Setting (SSL2P) */
    #define _00_RSPI_SSL2_POLARITY_LOW              (0x00U) /* SSL2 signal is active low */
    #define _04_RSPI_SSL2_POLARITY_HIGH             (0x04U) /* SSL2 signal is active high */
    /* SSL3 Signal Polarity Setting (SSL3P) */
    #define _00_RSPI_SSL3_POLARITY_LOW              (0x00U) /* SSL3 signal is active low */
    #define _08_RSPI_SSL3_POLARITY_HIGH             (0x08U) /* SSL3 signal is active high */
    
    /*
        RSPI Pin Control Register (SPPCR)
    */
    /* RSPI Loopback (SPLP) */
    #define _00_RSPI_LOOPBACK_DISABLED              (0x00U) /* Normal mode */
    #define _01_RSPI_LOOPBACK_ENABLED               (0x01U) /* Loopback mode (reversed transmit data = receive data) */
    /* RSPI Loopback 2 (SPLP2) */
    #define _00_RSPI_LOOPBACK2_DISABLED             (0x00U) /* Normal mode */
    #define _02_RSPI_LOOPBACK2_ENABLED              (0x02U) /* Loopback mode (transmit data = receive data) */
    /* MOSI Idle Fixed Value (MOIFV) */
    #define _00_RSPI_MOSI_LEVEL_LOW                 (0x00U) /* Level output on MOSIA during idling corresponds to low */
    #define _10_RSPI_MOSI_LEVEL_HIGH                (0x10U) /* Level output on MOSIA during idling corresponds to high */
    /* MOSI Idle Value Fixing Enable (MOIFE) */
    #define _00_RSPI_MOSI_FIXING_PREV_TRANSFER      (0x00U) /* MOSI output value equals final data from previous transfer */
    #define _20_RSPI_MOSI_FIXING_MOIFV_BIT          (0x20U) /* MOSI output value equals the value set in the MOIFV bit */
    
    /*
        RSPI Sequence Control Register (SPSCR)
    */
    /* RSPI Sequence Length Specification (SPSLN[2:0]) */
    #define _00_RSPI_SEQUENCE_LENGTH_1              (0x00U) /* 0 -> 0... */
    #define _01_RSPI_SEQUENCE_LENGTH_2              (0x01U) /* 0 -> 1 -> 0... */
    #define _02_RSPI_SEQUENCE_LENGTH_3              (0x02U) /* 0 -> 1 -> 2 -> 0... */
    #define _03_RSPI_SEQUENCE_LENGTH_4              (0x03U) /* 0 -> 1 -> 2 -> 3 -> 0... */
    #define _04_RSPI_SEQUENCE_LENGTH_5              (0x04U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 0... */
    #define _05_RSPI_SEQUENCE_LENGTH_6              (0x05U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 0... */
    #define _06_RSPI_SEQUENCE_LENGTH_7              (0x06U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 0... */
    #define _07_RSPI_SEQUENCE_LENGTH_8              (0x07U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 7 -> 0... */
    
    /*
        RSPI Data Control Register (SPDCR)
    */
    /* Number of Frames Specification (SPFC[1:0]) */
    #define _00_RSPI_FRAMES_1                       (0x00U) /* 1 frame */
    #define _01_RSPI_FRAMES_2                       (0x01U) /* 2 frames */
    #define _02_RSPI_FRAMES_3                       (0x02U) /* 3 frames */
    #define _03_RSPI_FRAMES_4                       (0x03U) /* 4 frames */
    /* RSPI Receive/Transmit Data Selection (SPRDTD) */
    #define _00_RSPI_READ_SPDR_RX_BUFFER            (0x00U) /* read SPDR values from receive buffer */
    #define _10_RSPI_READ_SPDR_TX_BUFFER            (0x10U) /* read SPDR values from transmit buffer (transmit buffer empty) */
    /* RSPI Longword Access/Word Access Specification (SPLW) */ 
    #define _00_RSPI_ACCESS_WORD                    (0x00U) /* SPDR is accessed in words */
    #define _20_RSPI_ACCESS_LONGWORD                (0x20U) /* SPDR is accessed in longwords */
    
    /*
        RSPI Clock Delay Register (SPCKD)
    */
    /* RSPCK Delay Setting (SCKDL[2:0]) */
    #define _00_RSPI_RSPCK_DELAY_1                  (0x00U) /* 1 RSPCK */
    #define _01_RSPI_RSPCK_DELAY_2                  (0x01U) /* 2 RSPCK */
    #define _02_RSPI_RSPCK_DELAY_3                  (0x02U) /* 3 RSPCK */
    #define _03_RSPI_RSPCK_DELAY_4                  (0x03U) /* 4 RSPCK */
    #define _04_RSPI_RSPCK_DELAY_5                  (0x04U) /* 5 RSPCK */
    #define _05_RSPI_RSPCK_DELAY_6                  (0x05U) /* 6 RSPCK */
    #define _06_RSPI_RSPCK_DELAY_7                  (0x06U) /* 7 RSPCK */
    #define _07_RSPI_RSPCK_DELAY_8                  (0x07U) /* 8 RSPCK */
    
    /*
        RSPI Slave Select Negation Delay Register (SSLND)
    */
    /* SSL Negation Delay Setting (SLNDL[2:0]) */
    #define _00_RSPI_SSL_NEGATION_DELAY_1           (0x00U) /* 1 RSPCK */
    #define _01_RSPI_SSL_NEGATION_DELAY_2           (0x01U) /* 2 RSPCK */
    #define _02_RSPI_SSL_NEGATION_DELAY_3           (0x02U) /* 3 RSPCK */
    #define _03_RSPI_SSL_NEGATION_DELAY_4           (0x03U) /* 4 RSPCK */
    #define _04_RSPI_SSL_NEGATION_DELAY_5           (0x04U) /* 5 RSPCK */
    #define _05_RSPI_SSL_NEGATION_DELAY_6           (0x05U) /* 6 RSPCK */
    #define _06_RSPI_SSL_NEGATION_DELAY_7           (0x06U) /* 7 RSPCK */
    #define _07_RSPI_SSL_NEGATION_DELAY_8           (0x07U) /* 8 RSPCK */
    
    /*
        RSPI Next-Access Delay Register (SPND)
    */
    /* RSPI Next-Access Delay Setting (SPNDL[2:0]) */
    #define _00_RSPI_NEXT_ACCESS_DELAY_1            (0x00U) /* 1 RSPCK + 2 PCLK */
    #define _01_RSPI_NEXT_ACCESS_DELAY_2            (0x01U) /* 2 RSPCK + 2 PCLK */
    #define _02_RSPI_NEXT_ACCESS_DELAY_3            (0x02U) /* 3 RSPCK + 2 PCLK */
    #define _03_RSPI_NEXT_ACCESS_DELAY_4            (0x03U) /* 4 RSPCK + 2 PCLK */
    #define _04_RSPI_NEXT_ACCESS_DELAY_5            (0x04U) /* 5 RSPCK + 2 PCLK */
    #define _05_RSPI_NEXT_ACCESS_DELAY_6            (0x05U) /* 6 RSPCK + 2 PCLK */
    #define _06_RSPI_NEXT_ACCESS_DELAY_7            (0x06U) /* 7 RSPCK + 2 PCLK */
    #define _07_RSPI_NEXT_ACCESS_DELAY_8            (0x07U) /* 8 RSPCK + 2 PCLK */
    
    /*
        RSPI Control Register 2 (SPCR2)
    */
    /* Parity Enable (SPPE) */
    #define _00_RSPI_PARITY_DISABLE                 (0x00U) /* Does not add parity bit to transmit data */
    #define _01_RSPI_PARITY_ENABLE                  (0x01U) /* Adds the parity bit to transmit data */
    /* Parity Mode (SPOE) */
    #define _00_RSPI_PARITY_EVEN                    (0x00U) /* Selects even parity for use in transmission and reception */
    #define _02_RSPI_PARITY_ODD                     (0x02U) /* Selects odd parity for use in transmission and reception */
    /* RSPI Idle Interrupt Enable (SPIIE) */
    #define _00_RSPI_IDLE_INTERRUPT_DISABLED        (0x00U) /* Disables the generation of RSPI idle interrupt */
    #define _04_RSPI_IDLE_INTERRUPT_ENABLED         (0x04U) /* Enables the generation of RSPI idle interrupt */
    /* Parity Self-Testing (PTE) */
    #define _00_RSPI_SELF_TEST_DISABLED             (0x00U) /* Disables the self-diagnosis function of the parity circuit */
    #define _08_RSPI_SELF_TEST_ENABLED              (0x08U) /* Enables the self-diagnosis function of the parity circuit */
    
    /*
        RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7)
    */
    /* RSPCK Phase Setting (CPHA) */
    #define _0000_RSPI_RSPCK_SAMPLING_ODD           (0x0000U) /* Data sampling on odd edge, data variation on even edge */
    #define _0001_RSPI_RSPCK_SAMPLING_EVEN          (0x0001U) /* Data variation on odd edge, data sampling on even edge */
    /* RSPCK Polarity Setting (CPOL) */
    #define _0000_RSPI_RSPCK_POLARITY_LOW           (0x0000U) /* RSPCK is low when idle */
    #define _0002_RSPI_RSPCK_POLARITY_HIGH          (0x0002U) /* RSPCK is high when idle */
    /* Bit Rate Division Setting (BRDV[1:0]) */
    #define _0000_RSPI_BASE_BITRATE_1               (0x0000U) /* These bits select the base bit rate */
    #define _0004_RSPI_BASE_BITRATE_2               (0x0004U) /* These bits select the base bit rate divided by 2 */
    #define _0008_RSPI_BASE_BITRATE_4               (0x0008U) /* These bits select the base bit rate divided by 4 */
    #define _000C_RSPI_BASE_BITRATE_8               (0x000CU) /* These bits select the base bit rate divided by 8 */
    /* SSL Signal Assertion Setting (SSLA[2:0]) */
    #define _0000_RSPI_SIGNAL_ASSERT_SSL0           (0x0000U) /* SSL0 */
    #define _0010_RSPI_SIGNAL_ASSERT_SSL1           (0x0010U) /* SSL1 */
    #define _0020_RSPI_SIGNAL_ASSERT_SSL2           (0x0020U) /* SSL2 */
    #define _0030_RSPI_SIGNAL_ASSERT_SSL3           (0x0030U) /* SSL3 */
    /* SSL Signal Level Keeping (SSLKP) */
    #define _0000_RSPI_SSL_KEEP_DISABLE             (0x0000U) /* Negates all SSL signals upon completion of transfer */
    #define _0080_RSPI_SSL_KEEP_ENABLE              (0x0080U) /* Keep SSL level from end of transfer till next access */
    /* RSPI Data Length Setting (SPB[3:0]) */
    #define _0400_RSPI_DATA_LENGTH_BITS_8           (0x0400U) /* 8 bits */
    #define _0800_RSPI_DATA_LENGTH_BITS_9           (0x0800U) /* 9 bits */
    #define _0900_RSPI_DATA_LENGTH_BITS_10          (0x0900U) /* 10 bits */
    #define _0A00_RSPI_DATA_LENGTH_BITS_11          (0x0A00U) /* 11 bits */
    #define _0B00_RSPI_DATA_LENGTH_BITS_12          (0x0B00U) /* 12 bits */
    #define _0C00_RSPI_DATA_LENGTH_BITS_13          (0x0C00U) /* 13 bits */
    #define _0D00_RSPI_DATA_LENGTH_BITS_14          (0x0D00U) /* 14 bits */
    #define _0E00_RSPI_DATA_LENGTH_BITS_15          (0x0E00U) /* 15 bits */
    #define _0F00_RSPI_DATA_LENGTH_BITS_16          (0x0F00U) /* 16 bits */
    #define _0000_RSPI_DATA_LENGTH_BITS_20          (0x0000U) /* 20 bits */
    #define _0100_RSPI_DATA_LENGTH_BITS_24          (0x0100U) /* 24 bits */
    #define _0200_RSPI_DATA_LENGTH_BITS_32          (0x0200U) /* 32 bits */
    /* RSPI LSB First (LSBF) */
    #define _0000_RSPI_MSB_FIRST                    (0x0000U) /* MSB first */
    #define _1000_RSPI_LSB_FIRST                    (0x1000U) /* LSB first */
    /* RSPI Next-Access Delay Enable (SPNDEN) */
    #define _0000_RSPI_NEXT_ACCESS_DELAY_DISABLE    (0x0000U) /* Next-access delay of 1 RSPCK + 2 PCLK */
    #define _2000_RSPI_NEXT_ACCESS_DELAY_ENABLE     (0x2000U) /* Next-access delay equal to setting of SPND register */
    /* SSL Negation Delay Setting Enable (SLNDEN) */
    #define _0000_RSPI_NEGATION_DELAY_DISABLE       (0x0000U) /* SSL negation delay of 1 RSPCK */
    #define _4000_RSPI_NEGATION_DELAY_ENABLE        (0x4000U) /* SSL negation delay equal to setting of SSLND register */
    /* RSPCK Delay Setting Enable (SCKDEN) */
    #define _0000_RSPI_RSPCK_DELAY_DISABLE          (0x0000U) /* RSPCK delay of 1 RSPCK */
    #define _8000_RSPI_RSPCK_DELAY_ENABLE           (0x8000U) /* RSPCK delay equal to setting of the SPCKD register */
    
    /*
        Interrupt Source Priority Register n (IPRn)
    */
    /* Interrupt Priority Level Select (IPR[3:0]) */
    #define _00_RSPI_PRIORITY_LEVEL0                (0x00U) /* Level 0 (interrupt disabled) */
    #define _01_RSPI_PRIORITY_LEVEL1                (0x01U) /* Level 1 */
    #define _02_RSPI_PRIORITY_LEVEL2                (0x02U) /* Level 2 */
    #define _03_RSPI_PRIORITY_LEVEL3                (0x03U) /* Level 3 */
    #define _04_RSPI_PRIORITY_LEVEL4                (0x04U) /* Level 4 */
    #define _05_RSPI_PRIORITY_LEVEL5                (0x05U) /* Level 5 */
    #define _06_RSPI_PRIORITY_LEVEL6                (0x06U) /* Level 6 */
    #define _07_RSPI_PRIORITY_LEVEL7                (0x07U) /* Level 7 */
    #define _08_RSPI_PRIORITY_LEVEL8                (0x08U) /* Level 8 */
    #define _09_RSPI_PRIORITY_LEVEL9                (0x09U) /* Level 9 */
    #define _0A_RSPI_PRIORITY_LEVEL10               (0x0AU) /* Level 10 */
    #define _0B_RSPI_PRIORITY_LEVEL11               (0x0BU) /* Level 11 */
    #define _0C_RSPI_PRIORITY_LEVEL12               (0x0CU) /* Level 12 */
    #define _0D_RSPI_PRIORITY_LEVEL13               (0x0DU) /* Level 13 */
    #define _0E_RSPI_PRIORITY_LEVEL14               (0x0EU) /* Level 14 */
    #define _0F_RSPI_PRIORITY_LEVEL15               (0x0FU) /* Level 15 (highest) */
    
    /***********************************************************************************************************************
    Macro definitions
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    Typedef definitions
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    Global functions
    ***********************************************************************************************************************/
    void R_RSPI0_Create(void);
    void R_RSPI0_Start(void);
    void R_RSPI0_Stop(void);
    MD_STATUS R_RSPI0_Send_Receive(uint32_t * const txbuf, uint16_t txnum, uint32_t * const rxbuf);
    static void r_rspi0_callback_transmitend(void);
    static void r_rspi0_callback_receiveend(void);
    static void r_rspi0_callback_error(uint8_t err_type);
    
    /* Start user code for function. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    #endif
    

    なお、これらのソースは以下の設定で生成させたものです。(e2 studioではなくCS+ですが。) [追記] ごめんなさい、スレーブ送信/受信機能に設定してしまったのは間違いだったかも知れないような気がしてきました。 → マスタ送信/受信機能に設定して生成し直したものを以下の3枚の画面コピーの下に張り直しました。ただ、ソースがペラペラであることを示す為のもので、FRAMと通信出来ることを意図したものではないです。 2017/05/17 23:24





    以下、生成し直したものです。

    r_cg_rspi.c

    1362.r_cg_rspi.c.2.txt
    /***********************************************************************************************************************
    * DISCLAIMER
    * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
    * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
    * applicable laws, including copyright laws. 
    * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
    * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
    * NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
    * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
    * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
    * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
    * of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
    * following link:
    * http://www.renesas.com/disclaimer
    *
    * Copyright (C) 2014, 2016 Renesas Electronics Corporation. All rights reserved.
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    * File Name    : r_cg_rspi.c
    * Version      : Code Generator for RX113 V1.02.05.01 [11 Nov 2016]
    * Device(s)    : R5F51138AxFP
    * Tool-Chain   : CCRX
    * Description  : This file implements device driver for RSPI module.
    * Creation Date: 2017/05/17
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    Pragma directive
    ***********************************************************************************************************************/
    /* Start user code for pragma. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    
    /***********************************************************************************************************************
    Includes
    ***********************************************************************************************************************/
    #include "r_cg_macrodriver.h"
    #include "r_cg_rspi.h"
    /* Start user code for include. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    #include "r_cg_userdefine.h"
    
    /***********************************************************************************************************************
    Global variables and functions
    ***********************************************************************************************************************/
    uint32_t * gp_rspi0_tx_address;         /* RSPI0 transmit buffer address */
    uint16_t   g_rspi0_tx_count;            /* RSPI0 transmit data number */
    uint32_t * gp_rspi0_rx_address;         /* RSPI0 receive buffer address */
    uint16_t   g_rspi0_rx_count;            /* RSPI0 receive data number */
    uint16_t   g_rspi0_rx_length;           /* RSPI0 receive data length */
    /* Start user code for global. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    
    /***********************************************************************************************************************
    * Function Name: R_RSPI0_Create
    * Description  : This function initializes the RSPI0 module.
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    void R_RSPI0_Create(void)
    {
        /* Disable RSPI interrupts */
        IEN(RSPI0,SPTI0) = 0U;
        IEN(RSPI0,SPRI0) = 0U;
        IEN(RSPI0,SPEI0) = 0U;
        IEN(RSPI0,SPII0) = 0U;
    
        /* Cancel RSPI module stop state */
        MSTP(RSPI0) = 0;
    
        /* Disable RSPI function */
        RSPI0.SPCR.BIT.SPE = 0U;
    
        /* Set control registers */
        RSPI0.SPPCR.BYTE = _00_RSPI_MOSI_FIXING_PREV_TRANSFER | _00_RSPI_LOOPBACK_DISABLED | _00_RSPI_LOOPBACK2_DISABLED;
        RSPI0.SPBR = _0F_RSPI0_DIVISOR;
        RSPI0.SPDCR.BYTE = _00_RSPI_ACCESS_WORD | _00_RSPI_FRAMES_1;
        RSPI0.SPSCR.BYTE = _00_RSPI_SEQUENCE_LENGTH_1;
        RSPI0.SPCKD.BYTE = _00_RSPI_RSPCK_DELAY_1;
        RSPI0.SSLND.BYTE = _00_RSPI_SSL_NEGATION_DELAY_1;
        RSPI0.SPND.BYTE = _00_RSPI_NEXT_ACCESS_DELAY_1;
        RSPI0.SPCR2.BYTE = _00_RSPI_PARITY_DISABLE;
        RSPI0.SPCMD0.WORD = _0001_RSPI_RSPCK_SAMPLING_EVEN | _0000_RSPI_RSPCK_POLARITY_LOW | _000C_RSPI_BASE_BITRATE_8 | 
                            _0000_RSPI_SIGNAL_ASSERT_SSL0 | _0000_RSPI_SSL_KEEP_DISABLE | _0400_RSPI_DATA_LENGTH_BITS_8 | 
                            _0000_RSPI_MSB_FIRST | _0000_RSPI_NEXT_ACCESS_DELAY_DISABLE | 
                            _0000_RSPI_NEGATION_DELAY_DISABLE | _0000_RSPI_RSPCK_DELAY_DISABLE;
    
        /* Set SPEI0, SPRI0, SPTI0 and SPII0 priority level */
        IPR(RSPI0,SPTI0) = _0F_RSPI_PRIORITY_LEVEL15;
    
        /* Set RSPCKA pin */
        MPC.P51PFS.BYTE = 0x0DU;
        PORT5.ODR0.BYTE &= 0xF3U;
        PORT5.PMR.BYTE |= 0x02U;
    
        /* Set MOSIA pin */
        MPC.P50PFS.BYTE = 0x0DU;
        PORT5.ODR0.BYTE &= 0xFCU;
        PORT5.PMR.BYTE |= 0x01U;
    
        /* Set MISOA pin */
        MPC.P52PFS.BYTE = 0x0DU;
        PORT5.ODR0.BYTE &= 0xCFU;
        PORT5.PMR.BYTE |= 0x04U;
    
        RSPI0.SPCR.BYTE = _01_RSPI_MODE_CLOCK_SYNCHRONOUS | _00_RSPI_FULL_DUPLEX_SYNCHRONOUS | _08_RSPI_MASTER_MODE;
    }
    
    /***********************************************************************************************************************
    * Function Name: R_RSPI0_Start
    * Description  : This function starts the RSPI0 module operation.
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    void R_RSPI0_Start(void)
    {
        volatile uint8_t dummy;
    
        /* Enable RSPI interrupts */
        IEN(RSPI0,SPTI0) = 1U;
        IEN(RSPI0,SPRI0) = 1U;
        IEN(RSPI0,SPEI0) = 1U;
        IEN(RSPI0,SPII0) = 1U;
    
        /* Clear error sources */
        dummy = RSPI0.SPSR.BYTE;
        RSPI0.SPSR.BYTE = 0xA0U;
    
        /* Disable idle interrupt */
        RSPI0.SPCR2.BIT.SPIIE = 0U;
    }
    
    /***********************************************************************************************************************
    * Function Name: R_RSPI0_Stop
    * Description  : This function stops the RSPI0 module operation.
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    void R_RSPI0_Stop(void)
    {
        /* Disable RSPI interrupts */
        IEN(RSPI0,SPTI0) = 0U;
        IEN(RSPI0,SPRI0) = 0U;
        IEN(RSPI0,SPEI0) = 0U;
        IEN(RSPI0,SPII0) = 0U;
    
        /* Disable RSPI function */
        RSPI0.SPCR.BIT.SPE = 0U;
    }
    /***********************************************************************************************************************
    * Function Name: R_RSPI0_Send_Receive
    * Description  : This function sends and receives RSPI0 data.
    * Arguments    : tx_buf -
    *                    transfer buffer pointer (not used when data is handled by DTC)
    *                tx_num -
    *                    buffer size
    *                rx_buf -
    *                    receive buffer pointer (not used when data is handled by DTC)
    * Return Value : status -
    *                    MD_OK or MD_ARGERROR
    ***********************************************************************************************************************/
    MD_STATUS R_RSPI0_Send_Receive(uint32_t * const tx_buf, uint16_t tx_num, uint32_t * const rx_buf)
    {
        MD_STATUS status = MD_OK;
    
        if (tx_num < 1U)
        {
            status = MD_ARGERROR;
        }
        else
        {
            /* Initialize the global counters */
            gp_rspi0_tx_address = tx_buf;
            g_rspi0_tx_count = tx_num;
            gp_rspi0_rx_address = rx_buf;
            g_rspi0_rx_length = tx_num;
            g_rspi0_rx_count = 0U;
    
            /* Enable transmit interrupt */
            RSPI0.SPCR.BIT.SPTIE = 1U;
    
            /* Enable receive interrupt */
            RSPI0.SPCR.BIT.SPRIE = 1U;
    
            /* Enable error interrupt */
            RSPI0.SPCR.BIT.SPEIE = 1U;
    
            /* Enable RSPI function */
            RSPI0.SPCR.BIT.SPE = 1U;
        }
    
        return (status);
    }
    
    /* Start user code for adding. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    


    r_cg_rspi_user.c

    4118.r_cg_rspi_user.c.2.txt
    /***********************************************************************************************************************
    * DISCLAIMER
    * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
    * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
    * applicable laws, including copyright laws. 
    * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
    * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
    * NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
    * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
    * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
    * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
    * of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
    * following link:
    * http://www.renesas.com/disclaimer
    *
    * Copyright (C) 2014, 2016 Renesas Electronics Corporation. All rights reserved.
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    * File Name    : r_cg_rspi_user.c
    * Version      : Code Generator for RX113 V1.02.05.01 [11 Nov 2016]
    * Device(s)    : R5F51138AxFP
    * Tool-Chain   : CCRX
    * Description  : This file implements device driver for RSPI module.
    * Creation Date: 2017/05/17
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    Pragma directive
    ***********************************************************************************************************************/
    /* Start user code for pragma. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    
    /***********************************************************************************************************************
    Includes
    ***********************************************************************************************************************/
    #include "r_cg_macrodriver.h"
    #include "r_cg_rspi.h"
    /* Start user code for include. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    #include "r_cg_userdefine.h"
    
    /***********************************************************************************************************************
    Global variables and functions
    ***********************************************************************************************************************/
    extern uint32_t * gp_rspi0_tx_address;         /* RSPI0 transmit buffer address */
    extern uint16_t   g_rspi0_tx_count;            /* RSPI0 transmit data number */
    extern uint32_t * gp_rspi0_rx_address;         /* RSPI0 receive buffer address */
    extern uint16_t   g_rspi0_rx_count;            /* RSPI0 receive data number */
    extern uint16_t   g_rspi0_rx_length;           /* RSPI0 receive data length */
    /* Start user code for global. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    
    /***********************************************************************************************************************
    * Function Name: r_rspi0_transmit_interrupt
    * Description  : None
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    #if FAST_INTERRUPT_VECTOR == VECT_RSPI0_SPTI0
    #pragma interrupt r_rspi0_transmit_interrupt(vect=VECT(RSPI0,SPTI0),fint)
    #else
    #pragma interrupt r_rspi0_transmit_interrupt(vect=VECT(RSPI0,SPTI0))
    #endif
    static void r_rspi0_transmit_interrupt(void)
    {
        uint16_t frame_cnt;
            
        for (frame_cnt = 0U; frame_cnt < (_00_RSPI_FRAMES_1 + 1U); frame_cnt++)
        {
            if (g_rspi0_tx_count > 0U)
            {
                /* Write data for transmission */
                RSPI0.SPDR.WORD.H = (*(uint16_t*)gp_rspi0_tx_address);
                gp_rspi0_tx_address++;
                g_rspi0_tx_count--;
            }
            else
            {
                /* Disable transmit interrupt */
                RSPI0.SPCR.BIT.SPTIE = 0U;
    
                /* Enable idle interrupt */
                RSPI0.SPCR2.BIT.SPIIE = 1U;
                break;
            }
        }
    }
    /***********************************************************************************************************************
    * Function Name: r_rspi0_receive_interrupt
    * Description  : None
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    #if FAST_INTERRUPT_VECTOR == VECT_RSPI0_SPRI0
    #pragma interrupt r_rspi0_receive_interrupt(vect=VECT(RSPI0,SPRI0),fint)
    #else
    #pragma interrupt r_rspi0_receive_interrupt(vect=VECT(RSPI0,SPRI0))
    #endif
    static void r_rspi0_receive_interrupt(void)
    {
        uint16_t frame_cnt;
        
        for (frame_cnt = 0U; frame_cnt < (_00_RSPI_FRAMES_1 + 1U); frame_cnt++)
        {
            if (g_rspi0_rx_length > g_rspi0_rx_count)
            {
                *(uint16_t *)gp_rspi0_rx_address = RSPI0.SPDR.WORD.H;
                gp_rspi0_rx_address++;
                g_rspi0_rx_count++;
    
                if (g_rspi0_rx_length == g_rspi0_rx_count)
                {
                    /* Disable receive interrupt */
                    RSPI0.SPCR.BIT.SPRIE = 0U;
                    r_rspi0_callback_receiveend();
                    break;
                }
            }
        }
    }
    /***********************************************************************************************************************
    * Function Name: r_rspi0_error_interrupt
    * Description  : None
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    #if FAST_INTERRUPT_VECTOR == VECT_RSPI0_SPEI0
    #pragma interrupt r_rspi0_error_interrupt(vect=VECT(RSPI0,SPEI0),fint)
    #else
    #pragma interrupt r_rspi0_error_interrupt(vect=VECT(RSPI0,SPEI0))
    #endif
    static void r_rspi0_error_interrupt(void)
    {
        uint8_t err_type;
    
        /* Disable RSPI function */
        RSPI0.SPCR.BIT.SPE = 0U;
    
        /* Disable transmit interrupt */
        RSPI0.SPCR.BIT.SPTIE = 0U;
    
        /* Disable receive interrupt */
        RSPI0.SPCR.BIT.SPRIE = 0U;
    
        /* Disable error interrupt */
        RSPI0.SPCR.BIT.SPEIE = 0U;
    
        /* Disable idle interrupt */
        RSPI0.SPCR2.BIT.SPIIE = 0U;
    
        /* Clear error sources */
        err_type = RSPI0.SPSR.BYTE;
        RSPI0.SPSR.BYTE = 0xA0U;
    
        if (err_type != 0U)
        {
            r_rspi0_callback_error(err_type);
        }
    }
    /***********************************************************************************************************************
    * Function Name: r_rspi0_idle_interrupt
    * Description  : None
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    #if FAST_INTERRUPT_VECTOR == VECT_RSPI0_SPII0
    #pragma interrupt r_rspi0_idle_interrupt(vect=VECT(RSPI0,SPII0),fint)
    #else
    #pragma interrupt r_rspi0_idle_interrupt(vect=VECT(RSPI0,SPII0))
    #endif
    static void r_rspi0_idle_interrupt(void)
    {
        /* Disable RSPI function */
        RSPI0.SPCR.BIT.SPE = 0U;
    
        /* Disable idle interrupt */
        RSPI0.SPCR2.BIT.SPIIE = 0U;
    
        r_rspi0_callback_transmitend();
    }
    /***********************************************************************************************************************
    * Function Name: r_rspi0_callback_transmitend
    * Description  : This function is a callback function when RSPI0 finishes transmission.
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    static void r_rspi0_callback_transmitend(void)
    {
        /* Start user code. Do not edit comment generated here */
        /* End user code. Do not edit comment generated here */
    }
    
    /***********************************************************************************************************************
    * Function Name: r_rspi0_callback_receiveend
    * Description  : This function is a callback function when RSPI0 finishes reception.
    * Arguments    : None
    * Return Value : None
    ***********************************************************************************************************************/
    static void r_rspi0_callback_receiveend(void)
    {
        /* Start user code. Do not edit comment generated here */
        /* End user code. Do not edit comment generated here */
    }
    
    /***********************************************************************************************************************
    * Function Name: r_rspi0_callback_error
    * Description  : This function is a callback function when RSPI0 error occurs.
    * Arguments    : err_type -
    *                    error type value
    * Return Value : None
    ***********************************************************************************************************************/
    static void r_rspi0_callback_error(uint8_t err_type)
    {
        /* Start user code. Do not edit comment generated here */
        /* End user code. Do not edit comment generated here */
    }
    
    
    /* Start user code for adding. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    


    r_cg_rspi.h

    7723.r_cg_rspi.h.2.txt
    /***********************************************************************************************************************
    * DISCLAIMER
    * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
    * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
    * applicable laws, including copyright laws. 
    * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
    * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
    * NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
    * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
    * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
    * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability 
    * of this software. By using this software, you agree to the additional terms and conditions found by accessing the 
    * following link:
    * http://www.renesas.com/disclaimer
    *
    * Copyright (C) 2014, 2016 Renesas Electronics Corporation. All rights reserved.
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    * File Name    : r_cg_rspi.h
    * Version      : Code Generator for RX113 V1.02.05.01 [11 Nov 2016]
    * Device(s)    : R5F51138AxFP
    * Tool-Chain   : CCRX
    * Description  : This file implements device driver for RSPI module.
    * Creation Date: 2017/05/17
    ***********************************************************************************************************************/
    #ifndef RSPI_H
    #define RSPI_H
    
    /***********************************************************************************************************************
    Macro definitions (Register bit)
    ***********************************************************************************************************************/
    /*
        RSPI Control Register (SPCR)
    */
    /* RSPI Mode Select (SPMS) */
    #define _00_RSPI_MODE_SPI                       (0x00U) /* SPI operation (four-wire method) */
    #define _01_RSPI_MODE_CLOCK_SYNCHRONOUS         (0x01U) /* Clock synchronous operation (three-wire method) */
    /* Communications Operating Mode Select (TXMD) */
    #define _00_RSPI_FULL_DUPLEX_SYNCHRONOUS        (0x00U) /* Full-duplex synchronous serial communications */
    #define _02_RSPI_TRANSMIT_ONLY                  (0x02U) /* Serial communications with transmit only operations */
    /* Mode Fault Error Detection Enable (MODFEN) */
    #define _00_RSPI_MODE_FAULT_DETECT_DISABLED     (0x00U) /* Disables the detection of mode fault error */
    #define _04_RSPI_MODE_FAULT_DETECT_ENABLED      (0x04U) /* Enables the detection of mode fault error */
    /* RSPI Master/Slave Mode Select (MSTR) */
    #define _00_RSPI_SLAVE_MODE                     (0x00U) /* Slave mode */
    #define _08_RSPI_MASTER_MODE                    (0x08U) /* Master mode */
    /* RSPI Error Interrupt Enable (SPEIE) */
    #define _00_RSPI_ERROR_INTERRUPT_DISABLED       (0x00U) /* Disables the generation of RSPI error interrupt */
    #define _10_RSPI_ERROR_INTERRUPT_ENABLED        (0x10U) /* Enables the generation of RSPI error interrupt */
    /* RSPI Transmit Interrupt Enable (SPTIE) */
    #define _00_RSPI_TRANSMIT_INTERRUPT_DISABLED    (0x00U) /* Disables the generation of RSPI transmit interrupt */
    #define _20_RSPI_TRANSMIT_INTERRUPT_ENABLED     (0x20U) /* Enables the generation of RSPI transmit interrupt */
    /* RSPI Function Enable (SPE) */
    #define _00_RSPI_FUNCTION_DISABLED              (0x00U) /* Disables the RSPI function */
    #define _40_RSPI_FUNCTION_ENABLED               (0x40U) /* Enables the RSPI function */
    /* RSPI Receive Interrupt Enable (SPRIE) */
    #define _00_RSPI_RECEIVE_INTERRUPT_DISABLED     (0x00U) /* Disables the generation of RSPI receive interrupt */
    #define _80_RSPI_RECEIVE_INTERRUPT_ENABLED      (0x80U) /* Enables the generation of RSPI receive interrupt */
    
    /*
        RSPI Slave Select Polarity Register (SSLP)
    */
    /* SSL0 Signal Polarity Setting (SSL0P) */
    #define _00_RSPI_SSL0_POLARITY_LOW              (0x00U) /* SSL0 signal is active low */
    #define _01_RSPI_SSL0_POLARITY_HIGH             (0x01U) /* SSL0 signal is active high */
    /* SSL1 Signal Polarity Setting (SSL1P) */
    #define _00_RSPI_SSL1_POLARITY_LOW              (0x00U) /* SSL1 signal is active low */
    #define _02_RSPI_SSL1_POLARITY_HIGH             (0x02U) /* SSL1 signal is active high */
    /* SSL2 Signal Polarity Setting (SSL2P) */
    #define _00_RSPI_SSL2_POLARITY_LOW              (0x00U) /* SSL2 signal is active low */
    #define _04_RSPI_SSL2_POLARITY_HIGH             (0x04U) /* SSL2 signal is active high */
    /* SSL3 Signal Polarity Setting (SSL3P) */
    #define _00_RSPI_SSL3_POLARITY_LOW              (0x00U) /* SSL3 signal is active low */
    #define _08_RSPI_SSL3_POLARITY_HIGH             (0x08U) /* SSL3 signal is active high */
    
    /*
        RSPI Pin Control Register (SPPCR)
    */
    /* RSPI Loopback (SPLP) */
    #define _00_RSPI_LOOPBACK_DISABLED              (0x00U) /* Normal mode */
    #define _01_RSPI_LOOPBACK_ENABLED               (0x01U) /* Loopback mode (reversed transmit data = receive data) */
    /* RSPI Loopback 2 (SPLP2) */
    #define _00_RSPI_LOOPBACK2_DISABLED             (0x00U) /* Normal mode */
    #define _02_RSPI_LOOPBACK2_ENABLED              (0x02U) /* Loopback mode (transmit data = receive data) */
    /* MOSI Idle Fixed Value (MOIFV) */
    #define _00_RSPI_MOSI_LEVEL_LOW                 (0x00U) /* Level output on MOSIA during idling corresponds to low */
    #define _10_RSPI_MOSI_LEVEL_HIGH                (0x10U) /* Level output on MOSIA during idling corresponds to high */
    /* MOSI Idle Value Fixing Enable (MOIFE) */
    #define _00_RSPI_MOSI_FIXING_PREV_TRANSFER      (0x00U) /* MOSI output value equals final data from previous transfer */
    #define _20_RSPI_MOSI_FIXING_MOIFV_BIT          (0x20U) /* MOSI output value equals the value set in the MOIFV bit */
    
    /*
        RSPI Sequence Control Register (SPSCR)
    */
    /* RSPI Sequence Length Specification (SPSLN[2:0]) */
    #define _00_RSPI_SEQUENCE_LENGTH_1              (0x00U) /* 0 -> 0... */
    #define _01_RSPI_SEQUENCE_LENGTH_2              (0x01U) /* 0 -> 1 -> 0... */
    #define _02_RSPI_SEQUENCE_LENGTH_3              (0x02U) /* 0 -> 1 -> 2 -> 0... */
    #define _03_RSPI_SEQUENCE_LENGTH_4              (0x03U) /* 0 -> 1 -> 2 -> 3 -> 0... */
    #define _04_RSPI_SEQUENCE_LENGTH_5              (0x04U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 0... */
    #define _05_RSPI_SEQUENCE_LENGTH_6              (0x05U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 0... */
    #define _06_RSPI_SEQUENCE_LENGTH_7              (0x06U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 0... */
    #define _07_RSPI_SEQUENCE_LENGTH_8              (0x07U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 7 -> 0... */
    
    /*
        RSPI Data Control Register (SPDCR)
    */
    /* Number of Frames Specification (SPFC[1:0]) */
    #define _00_RSPI_FRAMES_1                       (0x00U) /* 1 frame */
    #define _01_RSPI_FRAMES_2                       (0x01U) /* 2 frames */
    #define _02_RSPI_FRAMES_3                       (0x02U) /* 3 frames */
    #define _03_RSPI_FRAMES_4                       (0x03U) /* 4 frames */
    /* RSPI Receive/Transmit Data Selection (SPRDTD) */
    #define _00_RSPI_READ_SPDR_RX_BUFFER            (0x00U) /* read SPDR values from receive buffer */
    #define _10_RSPI_READ_SPDR_TX_BUFFER            (0x10U) /* read SPDR values from transmit buffer (transmit buffer empty) */
    /* RSPI Longword Access/Word Access Specification (SPLW) */ 
    #define _00_RSPI_ACCESS_WORD                    (0x00U) /* SPDR is accessed in words */
    #define _20_RSPI_ACCESS_LONGWORD                (0x20U) /* SPDR is accessed in longwords */
    
    /*
        RSPI Clock Delay Register (SPCKD)
    */
    /* RSPCK Delay Setting (SCKDL[2:0]) */
    #define _00_RSPI_RSPCK_DELAY_1                  (0x00U) /* 1 RSPCK */
    #define _01_RSPI_RSPCK_DELAY_2                  (0x01U) /* 2 RSPCK */
    #define _02_RSPI_RSPCK_DELAY_3                  (0x02U) /* 3 RSPCK */
    #define _03_RSPI_RSPCK_DELAY_4                  (0x03U) /* 4 RSPCK */
    #define _04_RSPI_RSPCK_DELAY_5                  (0x04U) /* 5 RSPCK */
    #define _05_RSPI_RSPCK_DELAY_6                  (0x05U) /* 6 RSPCK */
    #define _06_RSPI_RSPCK_DELAY_7                  (0x06U) /* 7 RSPCK */
    #define _07_RSPI_RSPCK_DELAY_8                  (0x07U) /* 8 RSPCK */
    
    /*
        RSPI Slave Select Negation Delay Register (SSLND)
    */
    /* SSL Negation Delay Setting (SLNDL[2:0]) */
    #define _00_RSPI_SSL_NEGATION_DELAY_1           (0x00U) /* 1 RSPCK */
    #define _01_RSPI_SSL_NEGATION_DELAY_2           (0x01U) /* 2 RSPCK */
    #define _02_RSPI_SSL_NEGATION_DELAY_3           (0x02U) /* 3 RSPCK */
    #define _03_RSPI_SSL_NEGATION_DELAY_4           (0x03U) /* 4 RSPCK */
    #define _04_RSPI_SSL_NEGATION_DELAY_5           (0x04U) /* 5 RSPCK */
    #define _05_RSPI_SSL_NEGATION_DELAY_6           (0x05U) /* 6 RSPCK */
    #define _06_RSPI_SSL_NEGATION_DELAY_7           (0x06U) /* 7 RSPCK */
    #define _07_RSPI_SSL_NEGATION_DELAY_8           (0x07U) /* 8 RSPCK */
    
    /*
        RSPI Next-Access Delay Register (SPND)
    */
    /* RSPI Next-Access Delay Setting (SPNDL[2:0]) */
    #define _00_RSPI_NEXT_ACCESS_DELAY_1            (0x00U) /* 1 RSPCK + 2 PCLK */
    #define _01_RSPI_NEXT_ACCESS_DELAY_2            (0x01U) /* 2 RSPCK + 2 PCLK */
    #define _02_RSPI_NEXT_ACCESS_DELAY_3            (0x02U) /* 3 RSPCK + 2 PCLK */
    #define _03_RSPI_NEXT_ACCESS_DELAY_4            (0x03U) /* 4 RSPCK + 2 PCLK */
    #define _04_RSPI_NEXT_ACCESS_DELAY_5            (0x04U) /* 5 RSPCK + 2 PCLK */
    #define _05_RSPI_NEXT_ACCESS_DELAY_6            (0x05U) /* 6 RSPCK + 2 PCLK */
    #define _06_RSPI_NEXT_ACCESS_DELAY_7            (0x06U) /* 7 RSPCK + 2 PCLK */
    #define _07_RSPI_NEXT_ACCESS_DELAY_8            (0x07U) /* 8 RSPCK + 2 PCLK */
    
    /*
        RSPI Control Register 2 (SPCR2)
    */
    /* Parity Enable (SPPE) */
    #define _00_RSPI_PARITY_DISABLE                 (0x00U) /* Does not add parity bit to transmit data */
    #define _01_RSPI_PARITY_ENABLE                  (0x01U) /* Adds the parity bit to transmit data */
    /* Parity Mode (SPOE) */
    #define _00_RSPI_PARITY_EVEN                    (0x00U) /* Selects even parity for use in transmission and reception */
    #define _02_RSPI_PARITY_ODD                     (0x02U) /* Selects odd parity for use in transmission and reception */
    /* RSPI Idle Interrupt Enable (SPIIE) */
    #define _00_RSPI_IDLE_INTERRUPT_DISABLED        (0x00U) /* Disables the generation of RSPI idle interrupt */
    #define _04_RSPI_IDLE_INTERRUPT_ENABLED         (0x04U) /* Enables the generation of RSPI idle interrupt */
    /* Parity Self-Testing (PTE) */
    #define _00_RSPI_SELF_TEST_DISABLED             (0x00U) /* Disables the self-diagnosis function of the parity circuit */
    #define _08_RSPI_SELF_TEST_ENABLED              (0x08U) /* Enables the self-diagnosis function of the parity circuit */
    
    /*
        RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7)
    */
    /* RSPCK Phase Setting (CPHA) */
    #define _0000_RSPI_RSPCK_SAMPLING_ODD           (0x0000U) /* Data sampling on odd edge, data variation on even edge */
    #define _0001_RSPI_RSPCK_SAMPLING_EVEN          (0x0001U) /* Data variation on odd edge, data sampling on even edge */
    /* RSPCK Polarity Setting (CPOL) */
    #define _0000_RSPI_RSPCK_POLARITY_LOW           (0x0000U) /* RSPCK is low when idle */
    #define _0002_RSPI_RSPCK_POLARITY_HIGH          (0x0002U) /* RSPCK is high when idle */
    /* Bit Rate Division Setting (BRDV[1:0]) */
    #define _0000_RSPI_BASE_BITRATE_1               (0x0000U) /* These bits select the base bit rate */
    #define _0004_RSPI_BASE_BITRATE_2               (0x0004U) /* These bits select the base bit rate divided by 2 */
    #define _0008_RSPI_BASE_BITRATE_4               (0x0008U) /* These bits select the base bit rate divided by 4 */
    #define _000C_RSPI_BASE_BITRATE_8               (0x000CU) /* These bits select the base bit rate divided by 8 */
    /* SSL Signal Assertion Setting (SSLA[2:0]) */
    #define _0000_RSPI_SIGNAL_ASSERT_SSL0           (0x0000U) /* SSL0 */
    #define _0010_RSPI_SIGNAL_ASSERT_SSL1           (0x0010U) /* SSL1 */
    #define _0020_RSPI_SIGNAL_ASSERT_SSL2           (0x0020U) /* SSL2 */
    #define _0030_RSPI_SIGNAL_ASSERT_SSL3           (0x0030U) /* SSL3 */
    /* SSL Signal Level Keeping (SSLKP) */
    #define _0000_RSPI_SSL_KEEP_DISABLE             (0x0000U) /* Negates all SSL signals upon completion of transfer */
    #define _0080_RSPI_SSL_KEEP_ENABLE              (0x0080U) /* Keep SSL level from end of transfer till next access */
    /* RSPI Data Length Setting (SPB[3:0]) */
    #define _0400_RSPI_DATA_LENGTH_BITS_8           (0x0400U) /* 8 bits */
    #define _0800_RSPI_DATA_LENGTH_BITS_9           (0x0800U) /* 9 bits */
    #define _0900_RSPI_DATA_LENGTH_BITS_10          (0x0900U) /* 10 bits */
    #define _0A00_RSPI_DATA_LENGTH_BITS_11          (0x0A00U) /* 11 bits */
    #define _0B00_RSPI_DATA_LENGTH_BITS_12          (0x0B00U) /* 12 bits */
    #define _0C00_RSPI_DATA_LENGTH_BITS_13          (0x0C00U) /* 13 bits */
    #define _0D00_RSPI_DATA_LENGTH_BITS_14          (0x0D00U) /* 14 bits */
    #define _0E00_RSPI_DATA_LENGTH_BITS_15          (0x0E00U) /* 15 bits */
    #define _0F00_RSPI_DATA_LENGTH_BITS_16          (0x0F00U) /* 16 bits */
    #define _0000_RSPI_DATA_LENGTH_BITS_20          (0x0000U) /* 20 bits */
    #define _0100_RSPI_DATA_LENGTH_BITS_24          (0x0100U) /* 24 bits */
    #define _0200_RSPI_DATA_LENGTH_BITS_32          (0x0200U) /* 32 bits */
    /* RSPI LSB First (LSBF) */
    #define _0000_RSPI_MSB_FIRST                    (0x0000U) /* MSB first */
    #define _1000_RSPI_LSB_FIRST                    (0x1000U) /* LSB first */
    /* RSPI Next-Access Delay Enable (SPNDEN) */
    #define _0000_RSPI_NEXT_ACCESS_DELAY_DISABLE    (0x0000U) /* Next-access delay of 1 RSPCK + 2 PCLK */
    #define _2000_RSPI_NEXT_ACCESS_DELAY_ENABLE     (0x2000U) /* Next-access delay equal to setting of SPND register */
    /* SSL Negation Delay Setting Enable (SLNDEN) */
    #define _0000_RSPI_NEGATION_DELAY_DISABLE       (0x0000U) /* SSL negation delay of 1 RSPCK */
    #define _4000_RSPI_NEGATION_DELAY_ENABLE        (0x4000U) /* SSL negation delay equal to setting of SSLND register */
    /* RSPCK Delay Setting Enable (SCKDEN) */
    #define _0000_RSPI_RSPCK_DELAY_DISABLE          (0x0000U) /* RSPCK delay of 1 RSPCK */
    #define _8000_RSPI_RSPCK_DELAY_ENABLE           (0x8000U) /* RSPCK delay equal to setting of the SPCKD register */
    
    /*
        Interrupt Source Priority Register n (IPRn)
    */
    /* Interrupt Priority Level Select (IPR[3:0]) */
    #define _00_RSPI_PRIORITY_LEVEL0                (0x00U) /* Level 0 (interrupt disabled) */
    #define _01_RSPI_PRIORITY_LEVEL1                (0x01U) /* Level 1 */
    #define _02_RSPI_PRIORITY_LEVEL2                (0x02U) /* Level 2 */
    #define _03_RSPI_PRIORITY_LEVEL3                (0x03U) /* Level 3 */
    #define _04_RSPI_PRIORITY_LEVEL4                (0x04U) /* Level 4 */
    #define _05_RSPI_PRIORITY_LEVEL5                (0x05U) /* Level 5 */
    #define _06_RSPI_PRIORITY_LEVEL6                (0x06U) /* Level 6 */
    #define _07_RSPI_PRIORITY_LEVEL7                (0x07U) /* Level 7 */
    #define _08_RSPI_PRIORITY_LEVEL8                (0x08U) /* Level 8 */
    #define _09_RSPI_PRIORITY_LEVEL9                (0x09U) /* Level 9 */
    #define _0A_RSPI_PRIORITY_LEVEL10               (0x0AU) /* Level 10 */
    #define _0B_RSPI_PRIORITY_LEVEL11               (0x0BU) /* Level 11 */
    #define _0C_RSPI_PRIORITY_LEVEL12               (0x0CU) /* Level 12 */
    #define _0D_RSPI_PRIORITY_LEVEL13               (0x0DU) /* Level 13 */
    #define _0E_RSPI_PRIORITY_LEVEL14               (0x0EU) /* Level 14 */
    #define _0F_RSPI_PRIORITY_LEVEL15               (0x0FU) /* Level 15 (highest) */
    
    /***********************************************************************************************************************
    Macro definitions
    ***********************************************************************************************************************/
    #define _0F_RSPI0_DIVISOR                       (0x0FU) /* SPBR(RSPI bit rate) register value */
    
    /***********************************************************************************************************************
    Typedef definitions
    ***********************************************************************************************************************/
    
    /***********************************************************************************************************************
    Global functions
    ***********************************************************************************************************************/
    void R_RSPI0_Create(void);
    void R_RSPI0_Start(void);
    void R_RSPI0_Stop(void);
    MD_STATUS R_RSPI0_Send_Receive(uint32_t * const txbuf, uint16_t txnum, uint32_t * const rxbuf);
    static void r_rspi0_callback_transmitend(void);
    static void r_rspi0_callback_receiveend(void);
    static void r_rspi0_callback_error(uint8_t err_type);
    
    /* Start user code for function. Do not edit comment generated here */
    /* End user code. Do not edit comment generated here */
    #endif
    







    以下、作り直した後のプロジェクトのファイル一式です。(すみません、e2 studioではなくCS+ですが。) (あくまで、ソースがペラペラであることを示す為のもので、FRAMと通信出来ることを意図したものではないです。)

    RX113_RSPI_ペラペラを示す一例です2.zip

  • In reply to NoMaY:

    ちなみに、R_RSPI0_Send_Receive()ですが、CS+のヘルプを見ても以下の画面コピーのように書かれているだけで、1バイト送信して1バイト受信する(一般化してNバイト送信してMバイト受信する)にはどうすれば良いのかピンと来ませんが、コード生成されたペラペラなソースを眺めていると、以下のような記述が目に入りますので、たぶん、こういう使い方なのだろうという予想はつきます。(ですので、それはあなたの推測に過ぎないでしょ、と突っ込まれると返す言葉が無いのですが、、、)

    (1) R_RSPI0_Send_Receive()の引数に送信バイト数の引数しかないものの、ソース中で受信バイト数 = 送信バイト数としていて、RSPIというのは結局のところシフトレジスタのシフト動作であることを思い起こすと、
      ・tx_num には 2 を設定する (N+M を設定する)
      ・tx_buf[0] は送信データ、tx_buf[1] は0x00なり0xffなりのダミーデータ (始めのNバイトが送信データ)
      ・rx_buf[0] はゴミデータ、rx_buf[1] が受信データ (終わりのMバイトが受信データ)
      だろうと思われる。

    (2) 送受信は割り込み駆動で行われ、
      ・受信完了時(rx_buf[0] と rx_buf[1] にデータが入った後)にr_rspi0_callback_receiveend()が呼ばれる
       (N+Mバイトのデータが入った後に)
      だろうと思われる。

    [追記] あれっ??? ソースとヘルプで引数の型が違うなぁ、、、[ここまで追記]

    r_cg_rspi.c

    MD_STATUS R_RSPI0_Send_Receive(uint32_t * const tx_buf, uint16_t tx_num, uint32_t * const rx_buf)
    {
        MD_STATUS status = MD_OK;

        if (tx_num < 1U)
        {
            status = MD_ARGERROR;
        }
        else
        {
            /* Initialize the global counters */
            gp_rspi0_tx_address = tx_buf;
            g_rspi0_tx_count = tx_num;
            gp_rspi0_rx_address = rx_buf;
            g_rspi0_rx_length = tx_num;
            g_rspi0_rx_count = 0U;

            /* Enable transmit interrupt */
            RSPI0.SPCR.BIT.SPTIE = 1U;

            /* Enable receive interrupt */
            RSPI0.SPCR.BIT.SPRIE = 1U;

            /* Enable error interrupt */
            RSPI0.SPCR.BIT.SPEIE = 1U;

            /* Enable RSPI function */
            RSPI0.SPCR.BIT.SPE = 1U;
        }

        return (status);
    }

    r_cg_rspi_user.c

    static void r_rspi0_receive_interrupt(void)
    {
        uint16_t frame_cnt;
        
        for (frame_cnt = 0U; frame_cnt < (_00_RSPI_FRAMES_1 + 1U); frame_cnt++)
        {
            if (g_rspi0_rx_length > g_rspi0_rx_count)
            {
                *(uint16_t *)gp_rspi0_rx_address = RSPI0.SPDR.WORD.H; ← [追記] これってrx_buf[●]の上位16bitが不定値になるのでは? [ここまで追記]
                gp_rspi0_rx_address++;
                g_rspi0_rx_count++;

                if (g_rspi0_rx_length == g_rspi0_rx_count)
                {
                    /* Disable receive interrupt */
                    RSPI0.SPCR.BIT.SPRIE = 0U;
                    r_rspi0_callback_receiveend();
                    break;
                }
            }
        }
    }